176 search results - page 30 / 36 » Performance improvement with circuit-level speculation |
MICRO
2002
IEEE
15 years 2 months ago
2002
IEEE
Register integration (or just integration) is a register renaming discipline that implements instruction reuse via physical register sharing. Initially developed to perform squash...
IEEEPACT
2000
IEEE
15 years 1 months ago
2000
IEEE
This paper describes the design of a dynamic branchpredictorfor a VLIW processor. The developed branch predictor predicts the direction of a branch, i.e., taken or not taken, and ...
ICS
1999
Tsinghua U.
15 years 1 months ago
1999
Tsinghua U.
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
—This paper presents a design space exploration of a selective load value prediction scheme suitable for energyaware Simultaneous Multi-Threaded (SMT) architectures. A load value...
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Voted
MICRO
1998
IEEE
15 years 1 months ago
1998
IEEE
Path profiles record the frequencies of execution paths through a program. Until now, the best global instruction schedulers have relied upon profile-gathered frequencies of condi...