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ASPLOS
1994
ACM
15 years 7 months ago
Compiler Optimizations for Improving Data Locality
In the past decade, processor speed has become significantly faster than memory speed. Small, fast cache memories are designed to overcome this discrepancy, but they are only effe...
Steve Carr, Kathryn S. McKinley, Chau-Wen Tseng
131
Voted
ACSC
2005
IEEE
15 years 9 months ago
Interprocedural Side-Effect Analysis and Optimisation in the Presence of Dynamic Class Loading
We introduce a new approach to computing interprocedural modification side effects for Java programs in the presence of dynamic class loading. When compile-time unknown classes c...
Phung Hua Nguyen, Jingling Xue
FPL
2009
Springer
79views Hardware» more  FPL 2009»
15 years 8 months ago
A reconfigurable architecture for the Phylogenetic Likelihood Function
As FPGA devices become larger, more coarse-grain modules coupled with large scale reconfigurable fabric become available, thus enabling new classes of applications to run effici...
Nikolaos Alachiotis, Alexandros Stamatakis, Euripi...
ICML
2010
IEEE
15 years 4 months ago
Boosting Classifiers with Tightened L0-Relaxation Penalties
We propose a novel boosting algorithm which improves on current algorithms for weighted voting classification by striking a better balance between classification accuracy and the ...
Noam Goldberg, Jonathan Eckstein
ASPLOS
2012
ACM
13 years 11 months ago
Path-exploration lifting: hi-fi tests for lo-fi emulators
Processor emulators are widely used to provide isolation and instrumentation of binary software. However they have proved difficult to implement correctly: processor specificati...
Lorenzo Martignoni, Stephen McCamant, Pongsin Poos...