151 search results - page 11 / 31 » Performance of Parallel Concatenated Coding Schemes |
80
Voted
LCPC
2001
Springer
15 years 4 months ago
2001
Springer
Abstract. We describe the structure of a compilation system that generates code for processor architectures supporting both explicit and implicit parallel threads. Such architectur...
JCP
2008
14 years 11 months ago
2008
An important issues in the design of interconnection networks for massively parallel computers is scalability. A new scalable interconnection network topology, called Double-Loop H...
104
Voted
ICCD
2006
IEEE
15 years 8 months ago
2006
IEEE
Pointer bugs associated with dynamically-allocated objects resulting in out-of-bounds memory access are an important class of software bugs. Because such bugs cannot be detected e...
85
Voted
ISCA
2000
IEEE
15 years 4 months ago
2000
IEEE
Speculative parallelization aggressively executes in parallel codes that cannot be fully parallelized by the compiler. Past proposals of hardware schemes have mostly focused on si...
VTC
2010
IEEE
14 years 10 months ago
2010
IEEE
—1 Hybrid Automatic Repeat reQuest (ARQ) plays an essential role in error control. Combining the incorrectly received packet replicas in hybrid ARQ has been shown to reduce the r...