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» Performance of Parallel Concatenated Coding Schemes
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IPPS
2006
IEEE
15 years 5 months ago
Analysis of checksum-based execution schemes for pipelined processors
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
Bernhard Fechner
ICS
2001
Tsinghua U.
15 years 4 months ago
Global optimization techniques for automatic parallelization of hybrid applications
This paper presents a novel technique to perform global optimization of communication and preprocessing calls in the presence of array accesses with arbitrary subscripts. Our sche...
Dhruva R. Chakrabarti, Prithviraj Banerjee
ICC
2007
IEEE
149views Communications» more  ICC 2007»
15 years 6 months ago
Reliability-based Partial Parallel Interference Cancellation and Iterative Decoding for DS-CDMA over Fading Channels
—Multistage Partial Parallel Interference Cancellation (PPIC) is proposed for Turbo-encoded DS-CDMA systems where the partial cancellation factors are derived based on the Loglik...
Ayman Elezabi
HPCA
2001
IEEE
16 years 1 days ago
CARS: A New Code Generation Framework for Clustered ILP Processors
Clustered ILP processors are characterized by a large number of non-centralized on-chip resources grouped into clusters. Traditional code generation schemes for these processors c...
Krishnan Kailas, Kemal Ebcioglu, Ashok K. Agrawala
CORR
2007
Springer
189views Education» more  CORR 2007»
14 years 11 months ago
Diversity-Multiplexing Tradeoff of Asynchronous Cooperative Diversity in Wireless Networks
Synchronization of relay nodes is an important and critical issue in exploiting cooperative diversity in wireless networks. In this paper, two asynchronous cooperative diversity s...
Shuangqing Wei