Sciweavers

4761 search results - page 938 / 953
» Performance of Protocols
Sort
View
MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
14 years 9 months ago
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin...
FMSD
2007
110views more  FMSD 2007»
14 years 9 months ago
Exploiting interleaving semantics in symbolic state-space generation
Symbolic techniques based on Binary Decision Diagrams (BDDs) are widely employed for reasoning about temporal properties of hardware circuits and synchronous controllers. However, ...
Gianfranco Ciardo, Gerald Lüttgen, Andrew S. ...
SIGARCH
2008
97views more  SIGARCH 2008»
14 years 9 months ago
SP-NUCA: a cost effective dynamic non-uniform cache architecture
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
Javier Merino, Valentin Puente, Pablo Prieto, Jos&...
SIGMETRICS
2008
ACM
161views Hardware» more  SIGMETRICS 2008»
14 years 9 months ago
Noncooperative power control and transmission scheduling in wireless collision channels
We consider a wireless collision channel, shared by a finite number of mobile users who transmit to a common base station using a random access protocol. Mobiles are selfoptimizin...
Ishai Menache, Nahum Shimkin
SIGMETRICS
2008
ACM
214views Hardware» more  SIGMETRICS 2008»
14 years 9 months ago
HMTT: a platform independent full-system memory trace monitoring system
Memory trace analysis is an important technology for architecture research, system software (i.e., OS, compiler) optimization, and application performance improvements. Many appro...
Yungang Bao, Mingyu Chen, Yuan Ruan, Li Liu, Jianp...