69 search results - page 5 / 14 » Performance of Switch Blocking on Multithreaded Architecture... |
DAC
2006
ACM
15 years 10 months ago
2006
ACM
In this paper, we present a methodology for low-cost and rapid context switch for multithreaded embedded processors with realtime guarantees. Context-switch, which involves saving...
100
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ISVLSI
2002
IEEE
15 years 2 months ago
2002
IEEE
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
GLOBECOM
2006
IEEE
15 years 3 months ago
2006
IEEE
As the Internet grows exponentially, scalable high performance routers and switches on backbone are required to provide a large number of ports, higher throughput, lower delay late...
163
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ASPLOS
2009
ACM
15 years 10 months ago
2009
ACM
Current shared memory multicore and multiprocessor systems are nondeterministic. Each time these systems execute a multithreaded application, even if supplied with the same input,...
NOCS
2009
IEEE
15 years 4 months ago
2009
IEEE
With the advent of Networks-on-Chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distrib...