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» Performance of Zebra Routing Software
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113
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CODES
2006
IEEE
15 years 7 months ago
Layout aware design of mesh based NoC architectures
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
Krishnan Srinivasan, Karam S. Chatha
97
Voted
CISIS
2008
IEEE
15 years 8 months ago
On the Potential of NoC Virtualization for Multicore Chips
As the end of Moores-law is on the horizon, power becomes a limiting factor to continuous increases in performance gains for single-core processors. Processor engineers have shifte...
Jose Flich, Samuel Rodrigo, José Duato, Tho...
LCTRTS
2010
Springer
14 years 11 months ago
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin,...
PADS
2003
ACM
15 years 7 months ago
Parallel Network Simulation under Distributed Genesis
We describe two major developments in the General Network Simulation Integration System (Genesis): the support for BGP protocol in large network simulations and distribution of th...
Boleslaw K. Szymanski, Yu Liu, Rashim Gupta
116
Voted
CODES
2008
IEEE
15 years 3 months ago
ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip
The performance of system-on-chip is determined not only by the performance of its functional units, but also by how efficiently they cooperate with one another. It is the on-chip...
Huaxi Gu, Jiang Xu, Zheng Wang