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143
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ISCA
2006
IEEE
92views Hardware» more  ISCA 2006»
15 years 3 months ago
Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing
The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The res...
Darshan D. Thaker, Tzvetan S. Metodi, Andrew W. Cr...
127
Voted
PPOPP
1990
ACM
15 years 7 months ago
Employing Register Channels for the Exploitation of Instruction Level Parallelism
Abstract - A multiprocessor system capable of exploiting fine-grained parallelism must support efficient synchronization and data passing mechanisms. This paper demonstrates the us...
Rajiv Gupta
208
Voted
ICDE
1999
IEEE
113views Database» more  ICDE 1999»
16 years 5 months ago
Parallel Algorithms for Computing Temporal Aggregates
The ability to model the temporal dimension is essential to many applications. Furthermore, the rate of increase in database size and response time requirements has outpaced advan...
Jose Alvin G. Gendrano, Bruce C. Huang, Jim M. Rod...
151
Voted
HIPC
2009
Springer
15 years 1 months ago
Fast checkpointing by Write Aggregation with Dynamic Buffer and Interleaving on multicore architecture
Large scale compute clusters continue to grow to ever-increasing proportions. However, as clusters and applications continue to grow, the Mean Time Between Failures (MTBF) has redu...
Xiangyong Ouyang, Karthik Gopalakrishnan, Tejus Ga...
136
Voted
ICS
1999
Tsinghua U.
15 years 8 months ago
Reorganizing global schedules for register allocation
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
Gang Chen, Michael D. Smith