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AINA
2006
IEEE
15 years 10 months ago
Accelerating the HMMER Sequence Analysis Suite Using Conventional Processors
Due to the ever-increasing size of sequence databases it has become clear that faster techniques must be employed to effectively perform biological sequence analysis in a reasonab...
John Paul Walters, Bashar Qudah, Vipin Chaudhary
PDP
2003
IEEE
15 years 9 months ago
On Using ZENTURIO for Performance and Parameter Studies on Cluster and Grid Architectures
Over the last decade, a dramatic increase has been observed in the need for generating and organising data in the course of large parameter studies, performance analysis, and soft...
Radu Prodan, Thomas Fahringer, Michael Geissler, G...
HPCA
2002
IEEE
16 years 4 months ago
Quantifying Load Stream Behavior
The increasing performance gap between processors and memory will force future architectures to devote significant resources towards removing and hiding memory latency. The two ma...
Suleyman Sair, Timothy Sherwood, Brad Calder
CLUSTER
2002
IEEE
15 years 9 months ago
Algorithmic Mechanism Design for Load Balancing in Distributed Systems
Computational Grids are large scale computing system composed of geographically distributed resources (computers, storage etc.) owned by self interested agents or organizations. T...
Daniel Grosu, Anthony T. Chronopoulos
DSD
2002
IEEE
90views Hardware» more  DSD 2002»
15 years 9 months ago
Simplifying Instruction Issue Logic in Superscalar Processors
Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instr...
Toshinori Sato, Itsujiro Arita