3321 search results - page 194 / 665 » Performance of parallel computations with dynamic processor ... |
130
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HIPC
1999
Springer
15 years 8 months ago
1999
Springer
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
115
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LFP
1994
15 years 5 months ago
1994
We present the rst system for estimating and using datadependent expression execution times in a language with rst-class procedures and imperative constructs. The presence of rst-...
131
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IPPS
2009
IEEE
15 years 10 months ago
2009
IEEE
A reduction is a computation in which a common operation, such as a sum, is to be performed across multiple pieces of data, each supplied by a separate task. We introduce phaser a...
131
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ICPP
2009
IEEE
15 years 1 months ago
2009
IEEE
Several multithreading techniques have been proposed to reduce the resource underutilization in Very Long Instruction Word (VLIW) processors. Simultaneous MultiThreading (SMT) is ...
144
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ICPP
2008
IEEE
15 years 10 months ago
2008
IEEE
A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, high-speed interface to increase the device density and ...