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ICCS
2005
Springer
15 years 10 months ago
Performance and Scalability Analysis of Cray X1 Vectorization and Multistreaming Optimization
Cray X1 Fortran and C/C++ compilers provide a number of loop transformations, notably vectorization and multistreaming, in order to exploit the multistreaming processor (MSP) hard...
Sadaf R. Alam, Jeffrey S. Vetter
ICCAD
2005
IEEE
131views Hardware» more  ICCAD 2005»
16 years 1 months ago
Code restructuring for improving cache performance of MPSoCs
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
Guilin Chen, Mahmut T. Kandemir
SECON
2007
IEEE
15 years 10 months ago
Quasi-static Centralized Rate Allocation for Sensor Networks
— Rate control for congestion mitigation and avoidance has received significant attention in the sensor networks literature. Existing rate control schemes dynamically assign rat...
Fang Bian, Sumit Rangwala, Ramesh Govindan
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 9 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
CCGRID
2004
IEEE
15 years 8 months ago
Lambda scheduling algorithm for file transfers on high-speed optical circuits
1 Scheduling resources on Grids is a well-known problem. The extension of Grids to LambdaGrids requires scheduling of lambdas, i.e., end-to-end high-speed circuits. In this paper, ...
Hua Lee, Malathi Veeraraghavan, Hojun Li, Edwin K....