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RT
2001
Springer
15 years 9 months ago
A Perceptually-Based Texture Caching Algorithm for Hardware-Based Rendering
: The performance of hardware-based interactive rendering systems is often constrained by polygon fill rates and texture map capacity, rather than polygon count alone. We present a...
Reynald Dumont, Fabio Pellacini, James A. Ferwerda
HPCA
2008
IEEE
16 years 5 months ago
Amdahl's Law in the multicore era
We apply Amdahl's Law to multicore chips using symmetric cores, asymmetric cores, and dynamic techniques that allows cores to work together on sequential execution. To Amdahl...
Mark D. Hill
CF
2010
ACM
15 years 10 months ago
Interval-based models for run-time DVFS orchestration in superscalar processors
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...
Georgios Keramidas, Vasileios Spiliopoulos, Stefan...
JSAT
2008
85views more  JSAT 2008»
15 years 4 months ago
Parallel SAT Solving using Bit-level Operations
We show how to exploit the 32/64 bit architecture of modern computers to accelerate some of the algorithms used in satisfiability solving by modifying assignments to variables in ...
Marijn Heule, Hans van Maaren
CF
2005
ACM
15 years 6 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen