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PPOPP
2009
ACM
16 years 5 months ago
An efficient transactional memory algorithm for computing minimum spanning forest of sparse graphs
Due to power wall, memory wall, and ILP wall, we are facing the end of ever increasing single-threaded performance. For this reason, multicore and manycore processors are arising ...
Seunghwa Kang, David A. Bader
ISCA
2011
IEEE
269views Hardware» more  ISCA 2011»
14 years 8 months ago
Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security
High assurance systems used in avionics, medical implants, and cryptographic devices often rely on a small trusted base of hardware and software to manage the rest of the system. ...
Mohit Tiwari, Jason Oberg, Xun Li 0001, Jonathan V...
AOSD
2007
ACM
15 years 9 months ago
A distributed dynamic aspect machine for scientific software development
This position paper proposes the use of an event-based dynamic AOP machine as an infrastructure for interactive development of high performance scientific software. Advice codes i...
Chanwit Kaewkasi, John R. Gurd
ICCAD
2003
IEEE
325views Hardware» more  ICCAD 2003»
15 years 10 months ago
Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading
While performance, area, and power constraints have been the driving force in designing current communication-enabled embedded systems, post-fabrication and run-time adaptability ...
Brian Swahn, Soha Hassoun
RTCSA
2006
IEEE
15 years 11 months ago
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors
To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constr...
Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu...