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142
Voted
ISCA
2000
IEEE
99views Hardware» more  ISCA 2000»
15 years 9 months ago
Transient fault detection via simultaneous multithreading
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
Steven K. Reinhardt, Shubhendu S. Mukherjee
SC
2003
ACM
15 years 10 months ago
Compiler Support for Exploiting Coarse-Grained Pipelined Parallelism
The emergence of grid and a new class of data-driven applications is making a new form of parallelism desirable, which we refer to as coarse-grained pipelined parallelism. This pa...
Wei Du, Renato Ferreira, Gagan Agrawal
123
Voted
HIPC
2003
Springer
15 years 10 months ago
Power-Aware Adaptive Issue Queue and Register File
In this paper, we present a novel technique to reduce dynamic and static power dissipation in the issue queue. The proposed scheme is based on delaying the dispatch of instructions...
Jaume Abella, Antonio González
ICS
1995
Tsinghua U.
15 years 8 months ago
On the Utility of Threads for Data Parallel Programming
Threads provide a useful programming model for asynchronous behavior because of their ability to encapsulate units of work that can then be scheduled for execution at runtime, bas...
Thomas Fahringer, Matthew Haines, Piyush Mehrotra
SBACPAD
2007
IEEE
129views Hardware» more  SBACPAD 2007»
15 years 11 months ago
Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications
The necessity of devising novel thread-level speculation (TLS) techniques has become extremely important with the growing acceptance of multi-core architectures by the industry. H...
Md. Mafijul Islam