Sciweavers

3321 search results - page 406 / 665
» Performance of parallel computations with dynamic processor ...
Sort
View
IJPP
2006
82views more  IJPP 2006»
15 years 4 months ago
Supporting Microthread Scheduling and Synchronisation in CMPs
Chip multiprocessors hold great promise for achieving scalability in future systems. Microthreaded chip multiprocessors add a means of exploiting legacy code in such systems. Usin...
Ian Bell, Nabil Hasasneh, Chris R. Jesshope
IPPS
2002
IEEE
15 years 9 months ago
Performance Prediction Technology for Agent-Based Resource Management in Grid Environments
Resource management constitutes an important infrastructural component of a computational grid environment. The aim of grid resource management is to efficiently schedule applicat...
Junwei Cao, Stephen A. Jarvis, Daniel P. Spooner, ...
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
16 years 5 months ago
Customization of Register File Banking Architecture for Low Power
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
146
Voted
ICS
1999
Tsinghua U.
15 years 9 months ago
Classifying load and store instructions for memory renaming
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...
Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary ...
PPOPP
2003
ACM
15 years 10 months ago
Impala: a middleware system for managing autonomic, parallel sensor systems
Sensor networks are long-running computer systems with many sensing/compute nodes working to gather information about their environment, process and fuse that information, and in ...
Ting Liu, Margaret Martonosi