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IPPS
2002
IEEE
15 years 9 months ago
Hierarchical Interconnects for On-Chip Clustering
In the sub-micron technology era, wire delays are becoming much more important than gate delays, making it particularly attractive to go for clustered designs. A common form of cl...
Aneesh Aggarwal, Manoj Franklin
EUROPAR
2009
Springer
15 years 8 months ago
Fast and Efficient Synchronization and Communication Collective Primitives for Dual Cell-Based Blades
The Cell Broadband Engine (Cell BE) is a heterogeneous multi-core processor specifically designed to exploit thread-level parallelism. Its memory model comprehends a common shared ...
Epifanio Gaona, Juan Fernández, Manuel E. A...
HPCA
2007
IEEE
16 years 4 months ago
A Scalable, Non-blocking Approach to Transactional Memory
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
Hassan Chafi, Jared Casper, Brian D. Carlstrom, Au...
CLUSTER
2009
IEEE
15 years 11 months ago
Combining I/O operations for multiple array variables in parallel netCDF
—Parallel netCDF (PnetCDF) is a popular library used in many scientific applications to store scientific datasets. It provides high-performance parallel I/O while maintaining ...
Kui Gao, Wei-keng Liao, Alok N. Choudhary, Robert ...
ISPASS
2005
IEEE
15 years 10 months ago
On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications
SIMD extensions are the most common technique used in current processors for multimedia computing. In order to obtain more performance for emerging applications SIMD extensions ne...
Friman Sánchez, Mauricio Alvarez, Esther Sa...