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WMPI
2004
ACM
15 years 9 months ago
Scalable cache memory design for large-scale SMT architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
Muhamed F. Mudawar
WIOPT
2010
IEEE
15 years 2 months ago
A contracts-based approach for spectrum sharing among cognitive radios
Abstract—Development of dynamic spectrum access and allocation techniques recently have made feasible the vision of cognitive radio systems. However, a fundamental question arise...
Dileep M. Kalathil, Rahul Jain
ASAP
2003
IEEE
124views Hardware» more  ASAP 2003»
15 years 9 months ago
Arbitrary Bit Permutations in One or Two Cycles
Symmetric-key block ciphers encrypt data, providing data confidentiality over the public Internet. For inter-operability reasons, it is desirable to support a variety of symmetric...
Zhijie Shi, Xiao Yang, Ruby B. Lee
IPPS
1998
IEEE
15 years 8 months ago
Efficient Fine-Grain Thread Migration with Active Threads
Thread migration is established as a mechanism for achieving dynamic load sharing. However, fine-grained migration has not been used due to the high thread and messaging overheads...
Boris Weissman, Benedict Gomes, Jürgen Quitte...
153
Voted
DAC
2009
ACM
16 years 5 months ago
Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis
In this paper, a design method for automotive architectures is proposed. The two main technical contributions are (i) a novel hardware/software architecture encoding that unifies ...
Jürgen Teich, Martin Lukasiewycz, Michael Gla...