Sciweavers

3321 search results - page 513 / 665
» Performance of parallel computations with dynamic processor ...
Sort
View
ISHPC
1999
Springer
15 years 8 months ago
Instruction-Level Microprocessor Modeling of Scientific Applications
Superscalar microprocessor efficiency is generally not as high as anticipated. In fact, sustained utilization below thirty percent of peak is not uncommon, even for fully optimized...
Kirk W. Cameron, Yong Luo, James Scharzmeier
IPPS
1998
IEEE
15 years 8 months ago
An Efficient RMS Admission Control and Its Application to Multiprocessor Scheduling
A real-time system must execute functionally correct computations in a timely manner. In order to guarantee that all tasks accepted in the system will meet their timing requiremen...
Sylvain Lauzac, Rami G. Melhem, Daniel Mossé...
IPPS
1998
IEEE
15 years 8 months ago
Optimizing Data Scheduling on Processor-in-Memory Arrays
In the study of PetaFlop project, Processor-In-Memory array was proposed to be a target architecture in achieving 1015 floating point operations per second computing performance. ...
Yi Tian, Edwin Hsing-Mean Sha, Chantana Chantrapor...
ANCS
2007
ACM
15 years 7 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos
LCTRTS
2010
Springer
15 years 5 months ago
An efficient code update scheme for DSP applications in mobile embedded systems
DSP processors usually provide dedicated address generation units (AGUs) to assist address computation. By carefully allocating variables in the memory, DSP compilers take advanta...
Weijia Li, Youtao Zhang