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ICPP
1987
IEEE
15 years 6 months ago
Performance of VLSI Engines for Lattice Computations
Abstract. We address the problem of designing and building efficient custom Vl.Sl-besed processors to do computations on large multi-dimensional lattices. The design tradeoffs for ...
Steven D. Kugelmass, Kenneth Steiglitz, Richard K....
ICPP
2008
IEEE
15 years 9 months ago
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
Xin Fu, Wangyuan Zhang, Tao Li, José A. B. ...
SIGMOD
2009
ACM
161views Database» more  SIGMOD 2009»
15 years 10 months ago
Dependency-aware reordering for parallelizing query optimization in multi-core CPUs
The state of the art commercial query optimizers employ cost-based optimization and exploit dynamic programming (DP) to find the optimal query execution plan (QEP) without evalua...
Wook-Shin Han, Jinsoo Lee
CORR
2010
Springer
179views Education» more  CORR 2010»
15 years 1 months ago
An Economic-based Resource Management and Scheduling for Grid Computing Applications
Resource management and scheduling plays a crucial role in achieving high utilization of resources in grid computing environments. Due to heterogeneity of resources, scheduling an...
G. Murugesan, C. Chellappan
ISCAPDCS
2007
15 years 4 months ago
Architectural requirements of parallel computational biology applications with explicit instruction level parallelism
—The tremendous growth in the information culture, efficient digital searches are needed to extract and identify information from huge data. The notion that evolution in silicon ...
Naeem Zafar Azeemi