3321 search results - page 555 / 665 » Performance of parallel computations with dynamic processor ... |
131
Voted
IPCCC
2006
IEEE
15 years 9 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
155
Voted
IEEEPACT
2006
IEEE
15 years 9 months ago
2006
IEEE
As chip multiprocessors (CMPs) become increasingly mainstream, architects have likewise become more interested in how best to share a cache hierarchy among multiple simultaneous t...
129
Voted
HPCA
2001
IEEE
16 years 3 months ago
2001
IEEE
The memory overhead introduced by directories constitutes a major hurdle in the scalability of cc-NUMA architectures, which makes the shared-memory paradigm unfeasible for very la...
117
Voted
RECONFIG
2009
IEEE
15 years 10 months ago
2009
IEEE
BLASTn is a ubiquitous tool used for large scale DNA analysis. Detailed profiling tests reveal that the most computationally intensive sections of the BLASTn algorithm are the sc...
130
Voted
AINA
2007
IEEE
15 years 9 months ago
2007
IEEE
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...