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HPCA
2012
IEEE
13 years 10 months ago
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chi
Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
Timothy N. Miller, Xiang Pan, Renji Thomas, Naser ...
ICDCS
2007
IEEE
15 years 9 months ago
mTreebone: A Hybrid Tree/Mesh Overlay for Application-Layer Live Video Multicast
Application-layer overlay networks have recently emerged as a promising solution for live media multicast on the Internet. A tree is probably the most natural structure for a mult...
Feng Wang, Yongqiang Xiong, Jiangchuan Liu
HPCA
1998
IEEE
15 years 7 months ago
PRISM: An Integrated Architecture for Scalable Shared Memory
This paper describes PRISM, a distributed sharedmemory architecture that relies on a tightly integrated hardware and operating system design for scalable and reliable performance....
Kattamuri Ekanadham, Beng-Hong Lim, Pratap Pattnai...
JUCS
2006
112views more  JUCS 2006»
15 years 3 months ago
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip
Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
ICPADS
2006
IEEE
15 years 9 months ago
Oriented Overlays For Clustering Client Requests To Data-Centric Network Services
Many of the data-centric network services deployed today hold massive volumes of data at their origin websites, and access the data to dynamically generate responses to user reque...
Congchun He, Vijay Karamcheti