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ISHPC
2003
Springer
15 years 8 months ago
Improving Memory Latency Aware Fetch Policies for SMT Processors
Abstract. In SMT processors several threads run simultaneously to increase available ILP, sharing but competing for resources. The instruction fetch policy plays a key role, determ...
Francisco J. Cazorla, Enrique Fernández, Al...
111
Voted
ICPPW
2006
IEEE
15 years 9 months ago
Performance Analysis of a Parallel Discrete Model for the Simulation of Laser Dynamics
This paper presents an analysis on the performance of a parallel implementation of a discrete model of laser dynamics, which is based on cellular automata. The performance of a 2D...
Jose Luis Guisado, Francisco Fernández de V...
IFL
2003
Springer
144views Formal Methods» more  IFL 2003»
15 years 8 months ago
Building an Interface Between Eden and Maple: A Way of Parallelizing Computer Algebra Algorithms
Eden is a parallel functional language extending Haskell with processes. This paper describes the implementation of an interface between the Eden language and the Maple system. The...
Rafael Martínez, Ricardo Pena
147
Voted
ICS
1993
Tsinghua U.
15 years 7 months ago
Dynamic Control of Performance Monitoring on Large Scale Parallel Systems
Performance monitoring of large scale parallel computers creates a dilemma: we need to collect detailed information to find performance bottlenecks, yet collecting all this data ...
Jeffrey K. Hollingsworth, Barton P. Miller
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
15 years 9 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin