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NOCS
2007
IEEE
15 years 9 months ago
Implementation and Evaluation of a Dynamically Routed Processor Operand Network
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...
Paul Gratz, Karthikeyan Sankaralingam, Heather Han...
VLSISP
2008
132views more  VLSISP 2008»
15 years 3 months ago
Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors
H.264/AVC is the latest video coding standard adopting variable block size motion estimation (VBS-ME), quarter-pixel accuracy, motion vector prediction and multi-reference frames f...
Brian M. H. Li, Philip Heng Wai Leong
134
Voted
SCCC
2005
IEEE
15 years 9 months ago
Balancing active objects on a peer to peer infrastructure
We present a contribution on dynamic load balancing for distributed and parallel object-oriented applications. We specially target on peer to peer systems and its capability to di...
Javier Bustos-Jiménez, Denis Caromel, Alexa...
162
Voted
IPPS
2010
IEEE
15 years 19 days ago
Scalable parallel I/O alternatives for massively parallel partitioned solver systems
Abstract--With the development of high-performance computing, I/O issues have become the bottleneck for many massively parallel applications. This paper investigates scalable paral...
Jing Fu, Ning Liu, Onkar Sahni, Kenneth E. Jansen,...
168
Voted
HPCA
1995
IEEE
15 years 7 months ago
The Effects of STEF in Finely Parallel Multithreaded Processors
The throughput of a multiple-pipelined processor suffers due to lack of sufficient instructions to make multiple pipelines busy and due to delays associated with pipeline depende...
Yamin Li, Wanming Chu