Sciweavers

1263 search results - page 218 / 253
» Performance of the IBM General Parallel File System
Sort
View
100
Voted
CC
2003
Springer
15 years 2 months ago
Early Control of Register Pressure for Software Pipelined Loops
Abstract. The register allocation in loops is generally performed after or during the software pipelining process. This is because doing a conventional register allocation at firs...
Sid Ahmed Ali Touati, Christine Eisenbeis
80
Voted
SASP
2008
IEEE
162views Hardware» more  SASP 2008»
15 years 4 months ago
Accelerating Compute-Intensive Applications with GPUs and FPGAs
—Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are F...
Shuai Che, Jie Li, Jeremy W. Sheaffer, Kevin Skadr...
ESA
1998
Springer
162views Algorithms» more  ESA 1998»
15 years 1 months ago
External Memory Algorithms
Abstract. Data sets in large applications are often too massive to t completely inside the computer's internal memory. The resulting input output communication or I O between ...
Jeffrey Scott Vitter
ICS
2009
Tsinghua U.
15 years 4 months ago
/scratch as a cache: rethinking HPC center scratch storage
To sustain emerging data-intensive scientific applications, High Performance Computing (HPC) centers invest a notable fraction of their operating budget on a specialized fast sto...
Henry M. Monti, Ali Raza Butt, Sudharshan S. Vazhk...
PLDI
2012
ACM
13 years 4 days ago
Adaptive input-aware compilation for graphics engines
While graphics processing units (GPUs) provide low-cost and efficient platforms for accelerating high performance computations, the tedious process of performance tuning required...
Mehrzad Samadi, Amir Hormati, Mojtaba Mehrara, Jan...