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TC
2010
14 years 8 months ago
Design and Analysis of On-Chip Networks for Large-Scale Cache Systems
—Switched networks have been adopted in on-chip communication for their scalability and efficient resource sharing. However, using a general network for a specific domain may res...
Yuho Jin, Eun Jung Kim, Ki Hwan Yum
HPCA
2009
IEEE
15 years 10 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
PIMRC
2008
IEEE
15 years 4 months ago
Performance evaluation of the MPE-iFEC Sliding RS Encoding for DVB-H streaming services
—This article studies the performance of the Sliding RS Encoding (SRSE) in the transmission of streaming services in DVB-H (Digital Video Broadcasting - Transmission System for H...
David Gozalvez, David Gomez-Barquero, Narcis Cardo...
ASPDAC
2011
ACM
217views Hardware» more  ASPDAC 2011»
14 years 1 months ago
Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core syst
This paper studies realization and performance comparison of the sequential and weak consistency models in the network-on-chip (NoC) based distributed shared memory (DSM) multi-cor...
Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jants...
ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
15 years 2 months ago
The MIT Alewife Machine: Architecture and Performance
Alewife is a multiprocessor architecture that supports up to 512 processing nodes connected over a scalable and cost-effective mesh network at a constant cost per node. The MIT Al...
Anant Agarwal, Ricardo Bianchini, David Chaiken, K...