111 search results - page 11 / 23 » Performance pathologies in hardware transactional memory |
104
Voted
APCSAC
2007
IEEE
15 years 3 months ago
2007
IEEE
Although they have been the main server technology for many years, multiprocessors are undergoing a renaissance due to multi-core chips and the attractive scalability properties of...
88
Voted
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
DATE
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
85
Voted
ISCA
2006
IEEE
15 years 3 months ago
2006
IEEE
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
89
Voted
IEEEPACT
2007
IEEE
15 years 3 months ago
2007
IEEE
With the advent of chip-multiprocessors, we are faced with the challenge of parallelizing performance-critical software. Transactional memory (TM) has emerged as a promising progr...