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» Performance pathologies in hardware transactional memory
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CASES
2004
ACM
15 years 3 months ago
Hardware assisted control flow obfuscation for embedded processors
+ With more applications being deployed on embedded platforms, software protection becomes increasingly important. This problem is crucial on embedded systems like financial transa...
Xiaotong Zhuang, Tao Zhang, Hsien-Hsin S. Lee, San...
CACM
2011
96views more  CACM 2011»
14 years 4 months ago
Why STM can be more than a research toy
Software Transactional Memory (STM) promises to simplify concurrent programming without requiring specific hardware support. Yet, STM’s credibility lies on the extent to which ...
Aleksandar Dragojevic, Pascal Felber, Vincent Gram...
PPOPP
2010
ACM
15 years 6 months ago
Is transactional programming actually easier?
Chip multi-processors (CMPs) have become ubiquitous, while tools that ease concurrent programming have not. The promise of increased performance for all applications through ever ...
Christopher J. Rossbach, Owen S. Hofmann, Emmett W...
110
Voted
ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
15 years 2 months ago
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery
We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At...
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, ...
SIGPLAN
2008
14 years 9 months ago
Single global lock semantics in a weakly atomic STM
As memory transactions have been proposed as a language-level replacement for locks, there is growing need for well-defined semantics. In contrast to database transactions, transa...
Vijay Menon, Steven Balensiefer, Tatiana Shpeisman...