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» Performance pathologies in hardware transactional memory
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ISPASS
2007
IEEE
15 years 3 months ago
Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events
This paper proposes the use of microprocessor performance counters for online measurement of complete system power consumption. While past studies have demonstrated the use of per...
W. Lloyd Bircher, Lizy K. John
ISCA
1998
IEEE
129views Hardware» more  ISCA 1998»
15 years 1 months ago
Memory System Characterization of Commercial Workloads
Commercial applications such as databases and Web servers constitute the largest and fastest-growing segment of the market for multiprocessor servers. Ongoing innovations in disk ...
Luiz André Barroso, Kourosh Gharachorloo, E...
EMSOFT
2006
Springer
15 years 1 months ago
Reliability mechanisms for file systems using non-volatile memory as a metadata store
Portable systems such as cell phones and portable media players commonly use non-volatile RAM (NVRAM) to hold all of their data and metadata, and larger systems can store metadata...
Kevin M. Greenan, Ethan L. Miller
IEEEPACT
2006
IEEE
15 years 3 months ago
A low-cost memory remapping scheme for address bus protection
The address sequence on the processor-memory bus can reveal abundant information about the control flow of a program. This can lead to critical information leakage such as encryp...
Lan Gao, Jun Yang 0002, Marek Chrobak, Youtao Zhan...
IEEEPACT
2005
IEEE
15 years 3 months ago
Characterization of TCC on Chip-Multiprocessors
Transactional Coherence and Consistency (TCC) is a novel coherence scheme for shared memory multiprocessors that uses programmer-defined transactions as the fundamental unit of p...
Austen McDonald, JaeWoong Chung, Hassan Chafi, Chi...