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» Performance pathologies in hardware transactional memory
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VIS
2007
IEEE
125views Visualization» more  VIS 2007»
15 years 10 months ago
High-Quality Multimodal Volume Rendering for Preoperative Planning of Neurosurgical Interventions
Surgical approaches tailored to an individual patient's anatomy and pathology have become standard in neurosurgery. Precise preoperative planning of these procedures, however,...
Johanna Beyer, Markus Hadwiger, Stefan Wolfsberg...
DAC
2008
ACM
15 years 10 months ago
Latency and bandwidth efficient communication through system customization for embedded multiprocessors
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
Chenjie Yu, Peter Petrov
MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
14 years 9 months ago
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin...
HPCA
2000
IEEE
15 years 1 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
ICCD
2008
IEEE
126views Hardware» more  ICCD 2008»
15 years 4 months ago
Accelerating search and recognition with a TCAM functional unit
Abstract— World data is increasing rapidly, doubling almost every three years[1][2]. To comprehend and use this data effectively, search and recognition (SR) applications will de...
Atif Hashmi, Mikko Lipasti