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ICPP
2005
IEEE
15 years 3 months ago
Peak Power Control for a QoS Capable On-Chip Network
In recent years integrating multiprocessors in a single chip is emerging for supporting various scientific and commercial applications, with diverse demands to the underlying on-c...
Yuho Jin, Eun Jung Kim, Ki Hwan Yum
ICCD
1999
IEEE
136views Hardware» more  ICCD 1999»
15 years 2 months ago
ActiveOS: Virtualizing Intelligent Memory
Current trends in DRAM memory chip fabrication have led many researchers to propose \intelligent memory" architectures that integrate microprocessors or logic with memory. Su...
Mark Oskin, Frederic T. Chong, Timothy Sherwood
MSE
2002
IEEE
135views Hardware» more  MSE 2002»
15 years 3 months ago
The Impact of SMT/SMP Designs on Multimedia Software Engineering - A Workload Analysis Study
This paper presents the study of running several core multimedia applications on a simultaneous multithreading (SMT) architecture and derives design principles for multimedia soft...
Yen-Kuang Chen, Rainer Lienhart, Eric Debes, Matth...
110
Voted
HOTI
2011
IEEE
13 years 9 months ago
iWISE: Inter-router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture
Abstract—Network-on-Chips (NoCs) paradigm is fast becoming a defacto standard for designing communication infrastructure for multicores with the dual goals of reducing power cons...
Dominic DiTomaso, Avinash Kodi, Savas Kaya, David ...
91
Voted
RAID
2009
Springer
15 years 4 months ago
Regular Expression Matching on Graphics Hardware for Intrusion Detection
The expressive power of regular expressions has been often exploited in network intrusion detection systems, virus scanners, and spam filtering applications. However, the flexibl...
Giorgos Vasiliadis, Michalis Polychronakis, Spyros...