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HPCA
2000
IEEE
15 years 2 months ago
Software-Controlled Multithreading Using Informing Memory Operations
Memorylatency isbecominganincreasingly importantperformance bottleneck, especially in multiprocessors. One technique for tolerating memory latency is multithreading, whereby we sw...
Todd C. Mowry, Sherwyn R. Ramkissoon
IPPS
1999
IEEE
15 years 2 months ago
Cashmere-VLM: Remote Memory Paging for Software Distributed Shared Memory
Software distributed shared memory (DSM) systems have successfully provided the illusion of shared memory on distributed memory machines. However, most software DSM systems use th...
Sandhya Dwarkadas, Robert Stets, Nikos Hardavellas...
BMCBI
2004
158views more  BMCBI 2004»
14 years 10 months ago
A novel Mixture Model Method for identification of differentially expressed genes from DNA microarray data
Background: The main goal in analyzing microarray data is to determine the genes that are differentially expressed across two types of tissue samples or samples obtained under two...
Kayvan Najarian, Maryam Zaheri, Ali Ajdari Rad, Si...
IPPS
2009
IEEE
15 years 4 months ago
Optimizing assignment of threads to SPEs on the cell BE processor
The Cell is a heterogeneous multicore processor that has attracted much attention in the HPC community. The bulk of the computational workload on the Cell processor is carried by ...
C. Devi Sudheer, T. Nagaraju, Pallav K. Baruah, As...
CF
2004
ACM
15 years 3 months ago
MaRS: a macro-pipelined reconfigurable system
We introduce MaRS, a reconfigurable, parallel computing engine with special emphasis on scalability, lending itself to the computation-/data-intensive multimedia data processing a...
Nozar Tabrizi, Nader Bagherzadeh, Amir Hosein Kama...