Sciweavers

2681 search results - page 365 / 537
» Performance results of running parallel applications on the ...
Sort
View
DAC
2008
ACM
15 years 11 months ago
Miss reduction in embedded processors through dynamic, power-friendly cache design
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
Garo Bournoutian, Alex Orailoglu
SYSTOR
2009
ACM
15 years 4 months ago
Transactifying Apache's cache module
Apache is a large-scale industrial multi-process and multithreaded application, which uses lock-based synchronization. We report on our experience in modifying Apache’s cache mo...
Haggai Eran, Ohad Lutzky, Zvika Guz, Idit Keidar
CONEXT
2009
ACM
14 years 11 months ago
Virtually eliminating router bugs
Software bugs in routers lead to network outages, security vulnerabilities, and other unexpected behavior. Rather than simply crashing the router, bugs can violate protocol semant...
Eric Keller, Minlan Yu, Matthew Caesar, Jennifer R...
TVLSI
2010
14 years 4 months ago
Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs
In many applications, a reduction of the amount of the original data or a representation of the original data by a small set of variables is often required. Among many techniques, ...
Christos-Savvas Bouganis, Iosifina Pournara, Peter...
ISPDC
2005
IEEE
15 years 3 months ago
On the Implementation and Evaluation of Berkeley Sockets on Maestro2 cluster computing environment
The support on cluster environments of ”legacy protocols” is important to avoid rewriting the code of applications, but this support should not prevent to achieve the maximum ...
Ricardo Guapo, Leonel Sousa, Shinichi Yamagiwa