2681 search results - page 372 / 537 » Performance results of running parallel applications on the ... |
ICPP
2003
IEEE
15 years 3 months ago
2003
IEEE
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...
ISCA
2002
IEEE
15 years 3 months ago
2002
IEEE
This paper introduces the idea of using a User-Level Memory Thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main ...
CASES
2009
ACM
15 years 4 months ago
2009
ACM
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
ICPP
2007
IEEE
15 years 4 months ago
2007
IEEE
The real-time image forming in future, high-end synthetic aperture radar systems is an example of an application that puts new demands on computer architectures. The initial quest...
EUROPAR
2005
Springer
15 years 3 months ago
2005
Springer
Large message latencies often lead to poor performance of parallel applications. In this paper, we investigate a latency-tolerating technique that immediately releases all blocking...