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DAC
2006
ACM
15 years 11 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
SBCCI
2005
ACM
123views VLSI» more  SBCCI 2005»
15 years 3 months ago
Fault tolerance overhead in network-on-chip flow control schemes
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer manageme...
Antonio Pullini, Federico Angiolini, Davide Bertoz...
SC
2000
ACM
15 years 2 months ago
Automatically Tuned Collective Communications
The performance of the MPI’s collective communications is critical in most MPI-based applications. A general algorithm for a given collective communication operation may not giv...
Sathish S. Vadhiyar, Graham E. Fagg, Jack Dongarra
ISCA
2011
IEEE
229views Hardware» more  ISCA 2011»
14 years 1 months ago
TLSync: support for multiple fast barriers using on-chip transmission lines
As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament ba...
Jungju Oh, Milos Prvulovic, Alenka G. Zajic
PPAM
2007
Springer
15 years 4 months ago
Cloth Simulation in the SILC Matrix Computation Framework: A Case Study
This paper presents a case study of numerical simulations in an easy-to-use matrix computation framework named Simple Interface for Library Collections (SILC), which allows users t...
Tamito Kajiyama, Akira Nukada, Reiji Suda, Hidehik...