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» Performance under Failures of DAG-based Parallel Computing
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HPCA
2000
IEEE
15 years 9 months ago
Improving the Throughput of Synchronization by Insertion of Delays
Efficiency of synchronization mechanisms can limit the parallel performance of many shared-memory applications. In addition, the ever increasing performance gap between processor...
Ravi Rajwar, Alain Kägi, James R. Goodman
136
Voted
EUROPAR
2005
Springer
15 years 10 months ago
Integrating Mobile Devices into the Grid: Design Considerations and Evaluation
Mobile devices increasingly offer functionality beyond the one provided by traditional resources – processor, memory and applications. This includes, for example, integrated mul...
Stavros Isaiadis, Vladimir Getov
119
Voted
ISPA
2004
Springer
15 years 10 months ago
A Fault Tolerance Protocol for Uploads: Design and Evaluation
This paper investigates fault tolerance issues in Bistro, a wide area upload architecture. In Bistro, clients first upload their data to intermediaries, known as bistros. A destin...
Leslie Cheung, Cheng-Fu Chou, Leana Golubchik, Yan...
CCGRID
2003
IEEE
15 years 10 months ago
Noncontiguous I/O Accesses Through MPI-IO
I/O performance remains a weakness of parallel computing systems today. While this weakness is partly attributed to rapid advances in other system components, I/O interfaces avail...
Avery Ching, Alok N. Choudhary, Kenin Coloma, Wei-...
ICPPW
2006
IEEE
15 years 11 months ago
Towards a Source Level Compiler: Source Level Modulo Scheduling
Modulo scheduling is a major optimization of high performance compilers wherein The body of a loop is replaced by an overlapping of instructions from different iterations. Hence ...
Yosi Ben-Asher, Danny Meisler