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87
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DAC
1993
ACM
15 years 5 months ago
Performance-Driven Interconnect Design Based on Distributed RC Delay Model
Jason Cong, Kwok-Shing Leung, Dian Zhou
103
Voted
ICCAD
1994
IEEE
131views Hardware» more  ICCAD 1994»
15 years 5 months ago
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
Hannah Honghua Yang, D. F. Wong
113
Voted
VLSID
1999
IEEE
93views VLSI» more  VLSID 1999»
15 years 5 months ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
Noel Menezes, Chung-Ping Chen
109
Voted
DAC
2000
ACM
16 years 2 months ago
On switch factor based analysis of coupled RC interconnects
We revisit a basic element of modern signal integrity analysis, the modeling of worst-case coupling capacitance effects within a switch factor (SF) based methodology. We show that...
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
104
Voted
ICCD
2004
IEEE
120views Hardware» more  ICCD 2004»
15 years 10 months ago
XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs
This paper describes XTalkDelay, an industrial-strength methodology and tool for measuring the impact of crosstalk on delays of paths in a design. The main cornerstone of XTalkDel...
Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwin...