23 search results - page 3 / 5 » Performance-Driven Interconnect Design Based on Distributed ... |
134
Voted
TCAD
1998
15 years 3 months ago
1998
— Conventional methods for optimal sizing of wires and transistors use linear resistor-capacitor (RC) circuit models and the Elmore delay as a measure of signal delay. If the RC ...
130
Voted
ICCAD
2002
IEEE
16 years 12 days ago
2002
IEEE
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system archite...
121
Voted
ISPD
2003
ACM
15 years 8 months ago
2003
ACM
: Recent years have seen significant research in finding closed form expressions for the delay of an RC circuit that improves upon the Elmore delay model. However, several of these...
163
Voted
CASES
2007
ACM
2007
ACM
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
15 years 7 months ago
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
118
Voted
ICCAD
2006
IEEE
16 years 13 days ago
2006
IEEE
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...