Sciweavers

436 search results - page 63 / 88
» Performance-Driven Processor Allocation
Sort
View
SP
1999
IEEE
125views Security Privacy» more  SP 1999»
15 years 1 months ago
A Multi-Threading Architecture for Multilevel Secure Transaction Processing
A TCB and security kernel architecture for supporting multi-threaded, queue-driven transaction processing applications in a multilevel secure environment is presented. Our design ...
Haruna R. Isa, William R. Shockley, Cynthia E. Irv...
93
Voted
ICPP
1997
IEEE
15 years 1 months ago
Automatic Parallelization and Scheduling of Programs on Multiprocessors using CASCH
r The lack of a versatile software tool for parallel program development has been one of the major obstacles for exploiting the potential of high-performance architectures. In this...
Ishfaq Ahmad, Yu-Kwong Kwok, Min-You Wu, Wei Shu
PARLE
1993
15 years 1 months ago
On the Performance of Parallel Join Processing in Shared Nothing Database Systems
: Parallel database systems aim at providing high throughput for OLTP transactions as well as short response times for complex and data-intensive queries. Shared nothing systems re...
Robert Marek, Erhard Rahm
72
Voted
SWAT
1992
Springer
111views Algorithms» more  SWAT 1992»
15 years 1 months ago
Retrieval of scattered information by EREW, CREW and CRCW PRAMs
The k-compaction problem arises when k out of n cells in an array are non-empty and the contents of these cells must be moved to the first k locations in the array. Parallel algori...
Faith E. Fich, Miroslaw Kowaluk, Krzysztof Lorys, ...
MICRO
1995
IEEE
97views Hardware» more  MICRO 1995»
15 years 1 months ago
Improving CISC instruction decoding performance using a fill unit
Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions ...
Mark Smotherman, Manoj Franklin