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» Performing time-sensitive network experiments
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DATE
2009
IEEE
183views Hardware» more  DATE 2009»
15 years 5 months ago
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips
Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on C...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...
MICRO
2009
IEEE
134views Hardware» more  MICRO 2009»
15 years 5 months ago
A case for dynamic frequency tuning in on-chip networks
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
Asit K. Mishra, Reetuparna Das, Soumya Eachempati,...
ASPDAC
2009
ACM
108views Hardware» more  ASPDAC 2009»
15 years 5 months ago
Synthesis of networks on chips for 3D systems on chips
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (N...
Srinivasan Murali, Ciprian Seiculescu, Luca Benini...
ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
15 years 2 months ago
Coherent Network Interfaces for Fine-Grain Communication
Historically, processor accesses to memory-mapped device registers have been marked uncachable to insure their visibility to the device. The ubiquity of snooping cache coherence, ...
Shubhendu S. Mukherjee, Babak Falsafi, Mark D. Hil...
MOBICOM
2005
ACM
15 years 4 months ago
Self-management in chaotic wireless deployments
Over the past few years, wireless networking technologies have made vast forays into our daily lives. Today, one can find 802.11 hardware and other personal wireless technology e...
Aditya Akella, Glenn Judd, Srinivasan Seshan, Pete...