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ICASSP
2011
IEEE
14 years 1 months ago
Reconfigurable decoder architectures for Raptor codes
Decoder architectures for architecture-aware Raptor codes having regular message access-and-processing patterns are presented. Raptor codes are a class of concatenated codes compo...
Hady Zeineddine, Mohammad M. Mansour
83
Voted
FUIN
2006
79views more  FUIN 2006»
14 years 9 months ago
Simple Gene Assembly Is Deterministic
We investigate in this paper a simple intramolecular model for gene assembly in ciliates. Unlike the general intramolecular model, the folds that a micronuclear chromosome may for...
Miika Langille, Ion Petre
80
Voted
GLOBECOM
2006
IEEE
15 years 3 months ago
Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any str...
Zhengya Zhang, Lara Dolecek, Borivoje Nikolic, Ven...
CORR
2006
Springer
127views Education» more  CORR 2006»
14 years 9 months ago
On the Peak-to-Mean Envelope Power Ratio of Phase-Shifted Binary Codes
The peak-to-mean envelope power ratio (PMEPR) of a code employed in orthogonal frequencydivision multiplexing (OFDM) systems can be reduced by permuting its coordinates and by rot...
Kai-Uwe Schmidt
CORR
2008
Springer
106views Education» more  CORR 2008»
14 years 9 months ago
Construction of Near-Optimum Burst Erasure Correcting Low-Density Parity-Check Codes
In this paper, a simple and effective tool for the design of low-density parity-check (LDPC) codes for iterative correction of bursts of erasures is presented. The design method co...
Enrico Paolini, Marco Chiani