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VLDB
2004
ACM
126views Database» more  VLDB 2004»
15 years 5 months ago
STEPS towards Cache-resident Transaction Processing
Online transaction processing (OLTP) is a multibillion dollar industry with high-end database servers employing state-of-the-art processors to maximize performance. Unfortunately,...
Stavros Harizopoulos, Anastassia Ailamaki
ACMMSP
2006
ACM
232views Hardware» more  ACMMSP 2006»
15 years 5 months ago
Implicit and explicit optimizations for stencil computations
Stencil-based kernels constitute the core of many scientific applications on block-structured grids. Unfortunately, these codes achieve a low fraction of peak performance, due pr...
Shoaib Kamil, Kaushik Datta, Samuel Williams, Leon...
103
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PPOPP
2003
ACM
15 years 4 months ago
Exploiting high-level coherence information to optimize distributed shared state
InterWeave is a distributed middleware system that supports the sharing of strongly typed, pointer-rich data structures across a wide variety of hardware architectures, operating ...
DeQing Chen, Chunqiang Tang, Brandon Sanders, Sand...
RTSS
2009
IEEE
15 years 6 months ago
Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores
—Memory accesses form an important source of timing unpredictability. Timing analysis of real-time embedded software thus requires bounding the time for memory accesses. Multipro...
Yan Li, Vivy Suhendra, Yun Liang, Tulika Mitra, Ab...
HPCA
2012
IEEE
13 years 7 months ago
Pacman: Tolerating asymmetric data races with unintrusive hardware
Data races are a major contributor to parallel software unreliability. A type of race that is both common and typically harmful is the Asymmetric data race. It occurs when at leas...
Shanxiang Qi, Norimasa Otsuki, Lois Orosa Nogueira...