Sciweavers

43 search results - page 5 / 9
» Physical Synthesis for CPLD Architectures
Sort
View
73
Voted
ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
15 years 6 months ago
Interconnect-aware high-level synthesis for low power
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
Lin Zhong, Niraj K. Jha
ASAP
2004
IEEE
119views Hardware» more  ASAP 2004»
15 years 1 months ago
Automatic Synthesis of Customized Local Memories for Multicluster Application Accelerators
Distributed local memories, or scratchpads, have been shown to effectively reduce cost and power consumption of application-specific accelerators while maintaining performance. Th...
Manjunath Kudlur, Kevin Fan, Michael L. Chu, Scott...
VLSID
2006
IEEE
129views VLSI» more  VLSID 2006»
15 years 10 months ago
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...
Saraju P. Mohanty, Elias Kougianos
DAC
1997
ACM
15 years 1 months ago
Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy
In this paper, we present a new integrated synthesis and partitioning method for multiple-FPGA applications. This method rst synthesizes a design speci cation in a ne-grained way ...
Wen-Jong Fang, Allen C.-H. Wu
101
Voted
DAC
2006
ACM
15 years 10 months ago
Behavior and communication co-optimization for systems with sequential communication media
In this paper we propose a new communication synthesis approach targeting systems with sequential communication media (SCM). Since SCMs require that the reading sequence and writi...
Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zh...