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NOCS
2010
IEEE
15 years 2 months ago
Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing
Nikita Nikitin, Satrajit Chatterjee, Jordi Cortade...
104
Voted
TVLSI
2010
14 years 10 months ago
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
Zhiyi Yu, Bevan M. Baas
98
Voted
ISCAS
2008
IEEE
109views Hardware» more  ISCAS 2008»
15 years 10 months ago
A low-area interconnect architecture for chip multiprocessors
— A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost and flexible routing capability. To achieve a low area cost, th...
Zhiyi Yu, Bevan M. Baas
141
Voted
CODES
2004
IEEE
15 years 7 months ago
Power-aware communication optimization for networks-on-chips with voltage scalable links
Networks-on-Chip (NoC) is emerging as a practical development platform for future systems-on-chip products. We propose an energyefficient static algorithm which optimizes the ener...
Dongkun Shin, Jihong Kim