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» Pipeline Timing Analysis Using a Trace-Driven Simulator
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MICRO
2002
IEEE
124views Hardware» more  MICRO 2002»
15 years 2 months ago
Optimizing pipelines for power and performance
During the concept phase and definition of next generation high-end processors, power and performance will need to be weighted appropriately to deliver competitive cost/performan...
Viji Srinivasan, David Brooks, Michael Gschwind, P...
76
Voted
CORR
2008
Springer
104views Education» more  CORR 2008»
14 years 9 months ago
Policies of System Level Pipeline Modeling
Pipelining is a well understood and often used implementation technique for increasing the performance of a hardware system. We develop several SystemC/C++ modeling techniques tha...
Edwin A. Harcourt
ICCD
2007
IEEE
120views Hardware» more  ICCD 2007»
15 years 6 months ago
Statistical timing analysis using Kernel smoothing
We have developed a new statistical timing analysis approach that does not impose any assumptions on the nature of manufacturing variability and takes into account an arbitrary mo...
Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwa...
78
Voted
ICCAD
2001
IEEE
185views Hardware» more  ICCAD 2001»
15 years 6 months ago
Application-Driven Processor Design Exploration for Power-Performance Trade-off Analysis
1 - This paper presents an efficient design exploration environment for high-end core processors. The heart of the proposed design exploration framework is a two-level simulation e...
Diana Marculescu, Anoop Iyer
DAC
2006
ACM
15 years 10 months ago
A real time budgeting method for module-level-pipelined bus based system using bus scenarios
In designing bus based systems with parallel and pipelined architecture, it is important to derive a real time budget (a specified execution time limit) for each task of a bus bas...
Tadaaki Tanimoto, Seiji Yamaguchi, Akio Nakata, Te...