1189 search results - page 11 / 238 » Pipeline Timing Analysis Using a Trace-Driven Simulator |
EUROPAR
2001
Springer
15 years 1 months ago
2001
Springer
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
84
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ISCC
2003
IEEE
15 years 2 months ago
2003
IEEE
In this paper, we propose new pipelined request-grant-accept (RGA) and request-grant (RG) maximal size matching (MSM) algorithms to achieve speedup in combined input and output qu...
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
: This paper presents a self-calibration method for designing high speed pipeline ADCs. Unlike all existing calibration algorithms, the proposed calibration does not insert any tes...
DAC
1994
ACM
15 years 1 months ago
1994
ACM
We present a systematic approach to synthesize an instruction set such that the given application software can be efficiently mapped to a parameterized, pipelined microarchitectur...
139
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FASE
2004
Springer
15 years 1 months ago
2004
Springer
Real-Time Maude is a language and tool supporting the formal specification and analysis of real-time and hybrid systems. The specification formalism is based on rewriting logic, em...