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» Pipeline Timing Analysis Using a Trace-Driven Simulator
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ASYNC
2000
IEEE
122views Hardware» more  ASYNC 2000»
15 years 9 months ago
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen...
IWNAS
2008
IEEE
15 years 11 months ago
A Novel Embedded Accelerator for Online Detection of Shrew DDoS Attacks
∗ As one type of stealthy and hard-to-detect attack, lowrate TCP-targeted DDoS attack can seriously throttle the throughput of normal TCP flows for a long time without being noti...
Hao Chen, Yu Chen
FSE
2004
Springer
90views Cryptology» more  FSE 2004»
15 years 10 months ago
Fast Software-Based Attacks on SecurID
SecurID is a widely used hardware token for strengthening authentication in a corporate environment. Recently, Biryukov, Lano, and Preneel presented an attack on the alleged SecurI...
Scott Contini, Yiqun Lisa Yin
ICML
1995
IEEE
16 years 5 months ago
Learning to Make Rent-to-Buy Decisions with Systems Applications
In the single rent-to-buy decision problem, without a priori knowledge of the amount of time a resource will be used we need to decide when to buy the resource, given that we can ...
P. Krishnan, Philip M. Long, Jeffrey Scott Vitter
ISVLSI
2007
IEEE
232views VLSI» more  ISVLSI 2007»
15 years 10 months ago
DSPstone Benchmark of CoDeL's Automated Clock Gating Platform
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
Nainesh Agarwal, Nikitas J. Dimopoulos