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» Pipeline Timing Analysis Using a Trace-Driven Simulator
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JSAC
2006
103views more  JSAC 2006»
14 years 11 months ago
Performance analysis of M-ary PPM TH-UWB systems in the presence of MUI and timing jitter
The symbol error probability (SEP) performance of time-hopping (TH) ultra-wideband (UWB) systems in the presence of multiuser interference (MUI) and timing jitter is considered wit...
N. V. Kokkalis, P. Takis Mathiopoulos, George K. K...
EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
15 years 4 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
TSMC
2010
14 years 6 months ago
On Robust Stability of Stochastic Genetic Regulatory Networks With Time Delays: A Delay Fractioning Approach
Robust stability serves as an important regulation mechanism in system biology and synthetic biology. In this paper, the robust stability analysis problem is investigated for a cla...
Yao Wang, Zidong Wang, Jinling Liang
VTS
2003
IEEE
89views Hardware» more  VTS 2003»
15 years 5 months ago
Diagnosis of Delay Defects Using Statistical Timing Models
— In this paper, we study the problem of delay defect diagnosis based on statistical timing models. We propose a diagnosis algorithm that can effectively utilize statistical timi...
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-...
RTAS
2005
IEEE
15 years 5 months ago
Timing Analysis for Sensor Network Nodes of the Atmega Processor Family
Low-end embedded architectures, such as sensor nodes, have become popular in diverse fields, many of which impose real-time constraints. Currently, the Atmel Atmega processor fam...
Sibin Mohan, Frank Mueller, David B. Whalley, Chri...