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APCCAS
2006
IEEE
373views Hardware» more  APCCAS 2006»
15 years 1 months ago
A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs
A new low offset dynamic comparator for high resolution high speed analog-to-digital application has been designed. Inputs are reconfigured from the typical differential pair compa...
Vipul Katyal, Randall L. Geiger, Degang Chen
87
Voted
ADBIS
2006
Springer
93views Database» more  ADBIS 2006»
15 years 3 months ago
An On-Line Reorganization Framework for SAN File Systems
While the cost per megabyte of magnetic disk storage is economical, organizations are alarmed by the increasing cost of managing storage. Storage Area Network (SAN) architectures ...
Shahram Ghandeharizadeh, Shan Gao, Chris Gahagan, ...
ICCAD
2000
IEEE
169views Hardware» more  ICCAD 2000»
15 years 1 months ago
Transistor-Level Timing Analysis Using Embedded Simulation
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...
Pawan Kulshreshtha, Robert Palermo, Mohammad Morta...
80
Voted
CODES
1998
IEEE
15 years 1 months ago
Software timing analysis using HW/SW cosimulation and instruction set simulator
Timing analysis for checking satisfaction of constraints is a crucial problem in real-time system design. In some current approaches, the delay of software modules is precalculate...
Jie Liu, Marcello Lajolo, Alberto L. Sangiovanni-V...
WSC
2007
14 years 11 months ago
Measuring manufacturing throughput using takt time analysis and simulation
This paper is motivated by a case study performed at a company that manufactures two main types of customized products. In an effort to significantly increase their throughput cap...
Jun Duanmu, Kevin Taaffe