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» Pipeline Vectorization for Reconfigurable Systems
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114
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FCCM
2007
IEEE
165views VLSI» more  FCCM 2007»
15 years 2 months ago
Sparse Matrix-Vector Multiplication Design on FPGAs
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV Solver ...
Junqing Sun, Gregory D. Peterson, Olaf O. Storaasl...
120
Voted
JRTIP
2008
300views more  JRTIP 2008»
15 years 6 days ago
Real-time human action recognition on an embedded, reconfigurable video processing architecture
Abstract In recent years, automatic human action recognition has been widely researched within the computer vision and image processing communities. Here we propose a realtime, emb...
Hongying Meng, Michael Freeman, Nick Pears, Chris ...
105
Voted
JCP
2008
119views more  JCP 2008»
15 years 6 days ago
Performance Comparisons, Design, and Implementation of RC5 Symmetric Encryption Core using Reconfigurable Hardware
With the wireless communications coming to homes and offices, the need to have secure data transmission is of utmost importance. Today, it is important that information is sent con...
Omar S. Elkeelany, Adegoke Olabisi
130
Voted
NIPS
2003
15 years 1 months ago
A Mixed-Signal VLSI for Real-Time Generation of Edge-Based Image Vectors
A mixed-signal image filtering VLSI has been developed aiming at real-time generation of edge-based image vectors for robust image recognition. A four-stage asynchronous median de...
Masakazu Yagi, Hideo Yamasaki, Tadashi Shibata
137
Voted
FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
15 years 13 days ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek