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» Pipelined Decomposable BSP Computers
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TC
2008
13 years 6 months ago
Self-Adaptive Configuration of Visualization Pipeline Over Wide-Area Networks
Next-generation scientific applications require the capability to visualize large archival data sets or on-going computer simulations of physical and other phenomena over wide-area...
Qishi Wu, Jinzhu Gao, Mengxia Zhu, Nageswara S. V....
ESTIMEDIA
2009
Springer
13 years 4 months ago
Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications
The increasing demand for low power and high performance multimedia embedded systems has motivated the need for effective solutions to satisfy application bandwidth and latency req...
Luis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, ...
VLSID
2007
IEEE
97views VLSI» more  VLSID 2007»
14 years 6 months ago
Efficient Microprocessor Verification using Antecedent Conditioned Slicing
We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardw...
Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraha...
JPDC
2007
96views more  JPDC 2007»
13 years 6 months ago
Optimal pipeline decomposition and adaptive network mapping to support distributed remote visualization
This paper discusses algorithmic and implementation aspects of a distributed remote visualization system that optimally decomposes and adaptively maps the visualization pipeline t...
Mengxia Zhu, Qishi Wu, Nageswara S. V. Rao, S. Sit...
HPCA
2006
IEEE
14 years 6 months ago
An approach for implementing efficient superscalar CISC processors
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E...